The present invention generally relates to a method of forming a semiconductor device, and more particularly, to a method of forming an insulated gate field effect transistor (MOSFET).
Generally a semiconductor integrated circuit often includes insulated gate field effect transistors as semiconductors. A semiconductor integrated circuit prevailed at present has problems of deterioration in transistor characteristics due to short channel effect such as dispersion of threshold voltage by variation in gate length, increase in leak current due to deterioration of subthreshold characteristics, which are caused by miniaturization of the devices.
In order to solve the problems, a shallow source/drain junction is known to be effective. Conventionally methods of
(1) reduction in source/drain implanting energies PA1 (2) control of diffusion on activation annealing with the use of rapid thermal annealing such as lamp heating or the like PA1 (3) formation of recess type elevated diffusion layer structure transistor PA1 (4) formation of poly Si pasting source drain diffusion layer structure PA1 (5) formation of locally elevated source/drain structure or the like
are effected for shallow junction formation.
For example, FIG. 8 shows a step for making an insulated gate field effect transistor by the adoption of the above described (4). As shown in FIG. 8(a), a gate insulation film 80, a gate electrode 82 having an oxide mask 85 are formed by a normal step on the surface of the Si substrate 81, and thereafter, oxide film side walls 83, 83 are formed on both the sides of a gate electrode 82 with deposition and anisotropy etch-back of oxide films. Then, a poly Si film 86 is deposited on it. As shown in FIG. 8(b), a photolithography operation is effected so as to provide resists R1, R1 in active regions (where the source/drain are formed) on both the sides of a gate electrode 82. As shown in FIG. 8(c), etching operation is effected with the resists R1, R1 as masks so as to form the pasting poly Si films 86a, 86a. Finally, an ion implantation operation is effect approximately vertically into the substrate surface as shown in FIG. 8(d) so as to continuously effect an activation annealing operation for forming source/drain diffusion layers 87, 87'.
FIG. 9 shows a step of making an insulated gate field effect transistor by adoption of the above described (5). As shown in FIG. 9(a), a gate insulation film 90 and a gate electrode 93 are formed by a normal step on a Si substrate 91. Thereafter, an oxidating operation is effected so as to form oxide films 92, 92 in the active regions on both the sides of the gate electrode 93, and also, oxide films 95 and 94, 94 respectively on the surface and both the side faces of the gate electrode 93. The photolithography operation is effected so as to have resists R2, R3, in a condition of spaced relation from the gate electrode 93, in the active regions of both the sides of the gate electrode 93. The oxide film 92 is etched with the resists R2, R2 and the oxide film on the gate electrode surface as masks so as to form opening portions .DELTA., .DELTA.' on both the sides of the gate electrode 92. Continuously, as shown in FIG. 9(b), the resists R2, R2 are removed, thereafter, doped poly Si (not shown) is deposited, on its entire face, on it so as to diffuse impurities, to be included in the above described doped poly Si on the substrate surface, by a thermal treating operation through the above described opening portions .DELTA., .DELTA.'. Local shallow source/drain diffusion layers 96, 96' are formed on both the sides of the gate electrode 93. Thereafter, an anisotropical etch-back operation is effected so as to form locally elevated layer side walls 97, 97 in electric contact with the local shallow source/drain diffusion layers 96, 96' on both the sides of the gate electrodes 93 (accurately oxide films 94, 94). As shown in FIG. 9(c), impurities are ion-implanted deeper than the depth of the above described local shallow source/drain diffusion layers 96, 96' approximately vertically on the substrate surface with the gate electrode 93 and locally elevated layer side walls 97, 97 as masks so as to form the source/drain diffusion layer 98, 98' coupled to both the sides of the above described local shallow source/drain diffusion layers 96, 96'. Finally, as shown in FIG. 9(d), a thermal treatment operation is effected so as to activate the implanted impurities.
Although a short channel effect can be restricted simply by realizing the shallow Junction of the source/drain, the diffusion layer resistance increases so as to deteriorate the performance of the devices. Such a problem exists in the shallow junction of the source/drain by the methods of the above described (1) through (2).
The above described (1) method has a bottom limit in energies which can be controlled with ion implanting energies. Low energies have a problem of extent of impurity ions by a channeling phenomenon. The reduction of diffusion layer depth is restricted so that the desired shallow Junction cannot be effected.
The method of the above described (2) has an effect in the restraint of the diffusion by the contraction of the diffusion time. When the ion implanting operation is used into the impurity implanting operation, the influences of the channeling cannot be avoided as in the above described (1). Therefore, the reduction of diffusion layer depth is restricted and the desired Junction cannot be effected.
In order to effect the shallow junction by the recess type structure of the above describe (3), a diffusion layer is formed in a layer upper than the channel face, a portion, which exists in a channel region, of the diffusion layer is removed by a recess etching operation, thereafter the poly Si is deposited on the whole face so as to form a gate electrode by a patterning, so that the channel region and the diffusion layer portion, the gate electrode cannot be formed for self-matching operation. Therefore, there are problems of increment of area by alignment margin, dispersion of characteristics by alignment shift, and so on. As the structure is of recess, difference from the normal process is larger. Further, there are problems such as etching damages of the channel portion, deterioration of flatness of the active region, and so on.
As the method of the above described (4) has a step of forming pasting poly Si films 86a, 86a on a layer upper than the substrate surface as described shown in FIG. 8, introducing impurities into the substrate 81 by diffusion from the poly Si films 86a, 86a and forming the source/drain diffusion layers 87, 87', this is extremely effective for shallow Junction formation without receiving the influences of the channeling at the introduction of the impurities, which is different from a case of the formation by the ion implanting operation. As the method is a normal process till the formation of the gate electrode 82, a problem to be caused due to the recess structure formation is not caused, which is different from a method of the above described (3). As the poly Si film 86 deposited on the whole face after the gate formation is patterned by a photolithographic operation, the pasting poly Si films 86a, 86a are hard to form due to the separation resolution limit and alignment shift of the source/drain in the miniaturization of the gate 82. As the pasting poly Si films 86a, 86a and the gate 82 (and active region) are not formed in self-aligned manner, which causes characteristic dispersion due to alignment shift, deterioration of packing density by the requirement of the alignment margin, and so on.
As the above described (5) method has a step of forming Junction 96, 96' closer to the channel with the diffusion from a layer upper than the substrate surface as shown in FIG. 9, it was effective in the shallow Junction formation as in the above described (4) method. Since it forms locally elevated layer side walls 97, 97 in self-aligned manner with respect to the gate 93, which is different from the above described (4) method, characteristics dispersion due to the alignment shift is not caused. When the thickness (thickness in a direction parallel to the substrate surface) of the locally elevated layer side walls 97, 97 is set smaller than the width of the opening portions .DELTA., .DELTA.' as shown in FIG. 9(b), the surface of the Si substrate 91 is etched by an over etching operation through the opening portions .DELTA., .DELTA.' in the formation of the locally elevated layer side walls 97, 97 by the anisotropical etch-back operation, thus causing leakage due to etching damages, increasing in Junction depth, and so on. In the worst case, the shallow Junction is completely etched, thus resulting in bad conduction. Since the width of the above described opening portions .DELTA., .DELTA.' is set slightly wider considering alignment shifts and so on accompanied by the photolithography when the thickness of the locally elevated layer side walls 97, 97 is set larger than the opening portions .DELTA., .DELTA.', freedom degree for selecting the thickness of the local accumulating layer side walls 97, 97 is reduced (thickness has to be increased). The locally elevated layer side walls 97, 97 in electric contact with the shallow junction is formed even on the gate electrode (not shown) on the isolation region. In order to remove the side walls on the isolation region so as to obtain the insulation of the source/drain, the photolithography and the etching are required for special use. As a result, the above described (5) method has the step of complicating the process and increasing the cost, because twice photolithography increases as compared with the normal process, in addition to the photolithography for forming the opening portions .DELTA., .DELTA.'.